STP3052D Datasheet, Stanson Technology

PIN CONFIGURATION (D-PAK) FEATURE TO-252 TO-251 -30V/-25.0A, RDS(ON) = 45mΩ (Typ.) @VGS = -10V -30V/-16.0A, RDS(ON.

STP3052D is the P-Channel logic enhancement mode power field effect transistor which is produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are pa.